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CPU structure: execution units and cache

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CPU structure: execution units and cache

In short: A modern CPU consists of several cores, each containing a control unit, execution units (ALU, FPU), registers and its own cache, plus a shared cache, a memory controller and connections to the other components.

In more detail: The CPU executes instructions: fetch, decode, execute, write back the result. To make this fast, the building blocks are arranged in several levels, from the tiny, super-fast register to the large, slower L3 cache.

In Depth

Components of a core:

  • Control unit: Fetches instructions, decodes them and controls the flow. This includes branch prediction, instruction queues and schedulers.
  • Execution units:
    • ALU (arithmetic logic unit): Integer arithmetic, comparisons, logic (addition, AND, shifting).
    • FPU (floating point unit): Decimal numbers.
    • Vector units (SSE, AVX, NEON): many values at once (SIMD), important for image, sound, AI.
    • Load/store units: Memory access.
  • Registers: Smallest, fastest memory directly in the execution unit (a few dozen to a hundred, 64 bits each). They hold numbers currently being calculated.
  • L1 and L2 cache: Per core, very small and fast.

Shared parts (uncore):

  • L3 cache: Shared by all cores.
  • Memory controller: Connects the CPU to main memory (DDR).
  • PCIe controller: Directly for graphics card and SSD.
  • Internal interconnect (ring, mesh, Infinity Fabric) between the cores.
  • Integrated graphics (iGPU) and media engines (on many models).
  • Security and power management: Clock, voltage, temperature.

Memory hierarchy (typical):

LevelSizeAccess time
Registers< 1 KB< 1 ns
L1 cache32 – 64 KB per core~1 ns
L2 cache0.5 – 2 MB per core~4 ns
L3 cache16 – 128 MB shared~10 ns
Main memory8 – 128 GB~80 ns
SSDterabytes~50,000 ns

Clock and performance: The clock (GHz) gives cycles per second. What really counts is clock × instructions per cycle (IPC) × core count.

Manufacturing: Billions of transistors in 3 to 10 nm technology on a silicon die. Heat (TDP) is removed by a cooler.

See also: CPU, L1, L2 and L3 cache, CPU pipeline

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